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To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices.
Renesas Technology Corp. Customer Support Dept. April 1, 2003
2002.9.3 Ver. 0.0
MITSUBISHI LSIs
M5M5W817KT - 70HI
8388608-BIT (524288-WORD BY 16-BIT / 10485776-WORD BY 8-BIT) CMOS STATIC RAM
DESCRIPTION
The M5M5W817KT is a f amily of low v oltage 8Mbit static RAMs organized as 524288-words by 16-bit / 1048576-words by 8-bit, f abricated by Mitsubishi's high-perf ormance 0.18m CMOS technology . The M5M5W817KT is suitable f or memory applications where a simple interf acing , battery operating and battery backup are the important design objectiv es. The M5M5W817KT is packaged in a 52pin-TSOP with the outline of 10.79mm x 10.49mm, and pin pitch of 0.40mm. It giv es the best solution f or a compaction of m ounting area as well as f lexibility of wiring pattern of printed circuit boards. The operating temperature range is -40 ~ +85C -
FEATURES
Single 2.7~3.6V power supply Small stand-by current: 0.1A (2.0V, ty p.) No clocks, No ref resh Data retention supply v oltage =2.0~3.6V All inputs and outputs are TTL compatible. Easy memory expansion by S1#, S2, BC1# and BC2# Common Data I/O Three-state outputs: OR-tie capability OE prev ents data contention in the I/O bus By te f unction (x8 mode) av ailable by By te# & A-1. Process technology : 0.18m CMOS Package: 52pin 10.79mm x 10.49mm TSOP [0.4mm pin pitch]
Operating temperature
Part name
Power Access time * Ty pical Ratings (max.) Supply max. 25C 40C 25C 40C 70C 85C
70ns 1.0 1.2 5 8 20 40
Stand-by c urrent
Icc1 (3.3V, Ty p.)
30mA (10MHz) 5mA (1MHz)
Active current
-40 ~ +85C
M5M5W817KT -70HI 2.7 ~ 3.6V
PIN CONFIGURATION
A15 A14 A13 A12 A11 A10 A9 A8 NC S1# W# NC NC VCC S2 NC NC A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 A16 BYTE# BC2# GND
* Typical parameter indicates the value for the center of distribution, and not 100% tested.
BC1# DQ16/A-1 DQ8 DQ15 DQ7 DQ14 DQ6 DQ13 DQ5 NC DQ12 DQ4 DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 OE# GND NC A0
Pin A0 ~ A18
Function Address input
DQ1 ~ DQ16 Data input / output Chip select input 1 S1# S2 W# OE# BC1# BC2# BYTE# Vcc GND Chip select input 2 Write control input Output enable input Lower By te (DQ1 ~ 8) Upper By te (DQ9 ~ 16) By te (x8 mode) enable input Power supply Ground supply
10.49mm
Outline: 52PTG-A N C : No Connection
1
2002.9.3 Ver. 0.0
MITSUBISHI LSIs
M5M5W817KT - 70HI
8388608-BIT (524288-WORD BY 16-BIT / 10485776-WORD BY 8-BIT) CMOS STATIC RAM
FUNCTION
The M5M5W817KT is organized as 524288-words by 16bit / 1048576-words by 8-bit. These dev ices operate on a single +2.7~3.6V power supply , and are directly TTL compatible to both input and output. Its f ully static circuit needs no clocks and no ref resh, and makes it usef ul. The operation mode are determined by a combination of the dev ice control inputs BC1# , BC2# , S1#, S2 , W#, OE# and BY TE#. Each mode is summarized in the f unction table. A write operation is executed whenev er the low lev el W# ov erlaps with the low lev el BC1# and/or BC2# and the low lev el S1# and the high lev el S2. The address (A-1~A18 : By te mode, A0~A18 : Word mode) must be set up bef ore the write cy c le and must be stable during the entire cy cle. A read operation is executed by s etting W# at a high lev el and OE# at a low lev el while BC1# and/or BC2# and S1#and S2 are in an activ e state (S1#=L, S2=H). When setting BYTE# at a low lev el, the f unction will be in the x8 mede, which is, DQ1-8 are av ailable and DQ9-16 are not av ailable. In the x8 mode, A-1 is used as the additional address. During the activ e f unction f or x8 mode, BC1# BC2# must be low lev el. When setting BC1# and BC2# at a high lev el or S1# at a high lev el or S2 at a low lev el, the chips are in a nonselectable mode in which both reading and writing are disabled. In this mode, the output stage is in a high-impedance state, allowing OR-tie with other chips and memory expansion by BC1#, BC2# and S1#, S2. The power supply c urrent is reduced as low as 0.1A (25C, ty pical), and the memory data can be held at +2.0V power supply , enabling battery back-up operation during power f ailure or power-down operation in the non-selected mode.
FUNCTION TABLE
S1# H X X L L L L L L L L L L L L S2 H L X H H H H H H H H H H H H BYTE# BC1# BC2# H or L H or L H H H H H H H H H H L L L X X H L L L H H H L L L L L L X X H H H H L L L L L L L L L W# X X X L H H L H H L H H L H H OE# X X X X L H X L X X L X X L H Mode Non selection Non selection Non selection Write Read ------Write Read ------Write Read ------Write Read ------DQ1~8 DQ9~15 High-Z High-Z High-Z Din Dout High-Z High-Z High-Z High-Z Din Dout High-Z Din Dout High-Z High-Z High-Z High-Z High-Z High-Z High-Z Din Dout High-Z Din Dout High-Z High-Z High-Z High-Z DQ16 High-Z High-Z High-Z High-Z High-Z High-Z Din Dout High-Z Din Dout High-Z A-1 A-1 A-1 Icc Standby Standby Standby Active Active Active Active Active Active Active Active Active Active Active Active
Note1 : "H" and "L" in this table mean VIH and VIL, respectiv ely . Note2 : "X" in this table should be "H" or "L".
2
2002.9.3 Ver. 0.0
MITSUBISHI LSIs
M5M5W817KT - 70HI
8388608-BIT (524288-WORD BY 16-BIT / 10485776-WORD BY 8-BIT) CMOS STATIC RAM
BLOCK DIAGRAM
8MS DQ1 A0 524288WORDS X 16 BITS or 1048576WORDS X 8 BITS
A18 S2 S1# BC1# BC2# BYTE#
DQ 8 DQ 9
CLOCK GENERATOR
DQ16 / A-1
x8/x16 Switching circuit
VCC GND
W# OE#
3
2002.9.3 Ver. 0.0
MITSUBISHI LSIs
M5M5W817KT - 70HI
8388608-BIT (524288-WORD BY 16-BIT / 10485776-WORD BY 8-BIT) CMOS STATIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Supply v oltage Input v oltage Output v oltage Power dissipation Operating temperature Storage temperature Conditions With respect to GND With respect to GND With respect to GND Ta = 25C Ratings Units
Vcc VI VO Pd Ta T stg
- 0.3* ~ +4.6 - 0.3* ~ Vcc + 0.3 (max. 4.6V) 0 ~ Vcc 700 -40 ~ +85 - 65 ~ +150
V mW
C C
* -3.0V in case of AC (Pulse width < 30ns) =
DC ELECTRICAL CHARACTERISTICS
Symbol
(Ta=-40~85C Vcc=2.7V~3.6V,unless otherwise noted) Conditions Limits Min 2.2 Ty p Max Vcc+0.2V Units
Parameter High-lev el input v oltage Low-lev el input v oltage
VIH VIL VOH VOL II IO Icc1 Icc2
IOH= - 0.5mA Low-lev el output v oltage IOL= 2.0mA Input leakage current VI =0 ~ Vcc
High-level output voltage
- 0.2 * 2.4
0.6 0.4 1 1 50 15 50 15 5 8 20 40 2.0
V
Output leakage current Activ e supply c urrent ( AC,MOS lev el ) Activ e supply c urrent ( AC,TTL lev el )
A
BC1# and BC2#=VIH or S1#=VIH or S2=VIL or OE#=VIH, VI/O=0 ~ Vcc BC1# and BC2# < 0.2V, S1# < 0.2V, S2 >Vcc-0.2V other inputs < 0.2V or > Vcc-0.2V Output - open (duty 100%)
f = 10MHz f = 1MHz f = 10MHz f = 1MHz ~ +25C ~ +40C ~ +70C ~ +85C
BC1# and BC2#=V IL , S1#=V IL ,S2=V IH other pins =V IH or VIL Output - open (duty 100%) (1) S1# > Vcc - 0.2V and S2 > Vcc - 0.2V,
BYTE# > Vcc - 0.2V or < 0.2V, other inputs = 0 ~ Vcc
-
30 5 30 5 1.0 1.2 -
mA
(2) S2 < 0.2V,
Icc3
Stand by s upply current ( AC,MOS lev el )
BYTE# > Vcc - 0.2V or < 0.2V, other inputs = 0 ~ Vcc
(3) BC1# and BC2# > Vcc - 0.2V
S1# < 0.2V, S2 > Vcc - 0.2V BYTE# > Vcc - 0.2V or < 0.2V, other inputs = 0 ~ Vcc
A
Icc4
Stand by s upply current ( AC,TTL lev el )
BC1# and BC2# =VIH or S1# =VIH or S2=VIL BYTE# > Vcc - 0.2V or < 0.2V, Other inputs= 0 ~ Vcc
mA
< =
30ns)
Note 3: Direction for current flowing into IC is indicated as positive (no mark) Note 4: Typical parameter indicates the value for the center of distribution at 3.0V, and not 100% tested.
* -1.0V in case of AC (Pulse width
CAPACITANCE (Ta=-40~+85C Vcc=2.7V~3.6V,unless otherwise noted)
Symbol Parameter Input capacitance Output capacitance Conditions Min VI=GND, VI=25mVrms, f =1MHz VO=GND,VO=25mVrms, f =1MHz Limits Ty p Max Units
CI CO
10 10
pF
4
2002.9.3 Ver. 0.0
MITSUBISHI LSIs
M5M5W817KT - 70HI
8388608-BIT (524288-WORD BY 16-BIT / 10485776-WORD BY 8-BIT) CMOS STATIC RAM
AC ELECTRICAL CHARACTERISTICS (Ta=-40~+85C, Vcc=2.7V~3.6V,unless otherwise noted) (1) TEST CONDITIONS
2.7~3.6V Input pulse VIH=2.7V, VIL=0.2V Input rise time and f all time 5ns
Supply v oltage Ref erence lev el Output loads
1TTL DQ CL
Including scope and jig capacitance
VOH=VOL=1.5V
Transition is measured 200mV from steady state voltage.(for ten,tdis)
Fig.1,CL=30pF CL=5pF (for ten,tdis)
Fig.1 Output load
(2) READ CYCLE
Symbol tCR Parameter Read cy cle time Address access time Chip select 1 access time Chip select 2 access time By te control 1 access time By te control 2 access time Output enable access time Output disable time af t er S1# high Output disable time af t er S2 low Output disable time af t er BC1# high Output disable time af t er BC2# high Output disable time af t er OE# high Output enable time af ter S1# low Output enable time af ter S2 high Output enable time af ter BC1# low Output enable time af ter BC2# low Output enable time af ter OE# low Data v alid time after address Limits 70HI Min 70 Max 70 70 70 70 70 35 25 25 25 25 25 10 10 5 5 5 10 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Units
ta(A) ta(S1) ta(S2) ta(BC1) ta(BC2) ta(OE) tdis (S1) tdis (S2) tdis (BC1) tdis (BC2) tdis (OE) ten(S1) ten(S2) ten(BC1) ten(BC2) ten(OE) tV(A)
(3) WRITE CYCLE
Symbol Parameter Write cy cle time Write pulse width Address setup time Address setup time with respect to W# By te control 1 setup time By te control 2 setup time Chip select 1 setup time Chip select 2 setup time Data setup time Data hold time Write recov ery time Output disable time f rom W# low Output disable time f rom OE# high Output enable time f rom W# high Output enable time f rom OE# low Limits 70HI Min 70 55 0 65 65 65 65 65 35 0 0 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Units
tCW tw(W) tsu(A) tsu(A-WH) tsu(BC1) tsu(BC2) tsu(S1) tsu(S2) tsu(D) th(D) trec(W) tdis (W) tdis (OE) ten(W) ten(OE)
25 25 5 5
5
2002.9.3 Ver. 0.0
MITSUBISHI LSIs
M5M5W817KT - 70HI
8388608-BIT (524288-WORD BY 16-BIT / 10485776-WORD BY 8-BIT) CMOS STATIC RAM
(4) Byte# function
Symbol Limits Parameter BYTE# set up time BYTE# recov ery time Test conditions Min Ty p Max Units ms ms
tsu (BYTE) trec (BYTE)
5 5
(5) TIMING DIAGRAMS BYTE#
S2 S1# tsu (BYTE) BYTE# trec (BYTE)
Read cycle
A0~18
(Word Mode)
tCR
A-1~18
(Byte Mode)
ta(A) ta(BC1) or ta(BC2)
(Note5)
tv (A)
BC1#, BC2#
tdis (BC1) or tdis (BC2) ta(S1)
(Note5)
S1#
(Note5)
tdis (S1) ta(S2)
(Note5)
S2
(Note5)
tdis (S2) ta (OE)
(Note5)
OE#
(Note5) W# = "H" lev el
ten (OE) ten (BC1) ten (BC2) ten (S1) ten (S2)
tdis (OE)
(Note5)
DQ1~16
(Word Mode)
DQ1~8
(Byte Mode)
VALID DATA
6
2002.9.3 Ver. 0.0
MITSUBISHI LSIs
M5M5W817KT - 70HI
8388608-BIT (524288-WORD BY 16-BIT / 10485776-WORD BY 8-BIT) CMOS STATIC RAM
Write cycle( W# control mode )
A0~18
(Word Mode)
tCW
A-1~18
(Byte Mode)
tsu (BC1) or tsu(BC2)
BC1#, BC2#
(Note5) (Note5)
S1#
(Note5)
tsu (S1)
(Note5)
S2
(Note5)
tsu (S2)
(Note5)
OE# tsu (A) W# DQ1~16
(Word Mode)
tsu (A-WH) tw (W) tdis (W)
trec (W) ten(OE) ten (W)
tdis(OE)
DATA IN STABLE
DQ1~8
(Byte Mode)
tsu (D) tCW
th (D)
Write cycle (BC# control mode)
A0~18
(Word Mode)
A-1~18
(Byte Mode)
BC1#, BC2# S1#
(Note5)
tsu (A)
tsu (BC1) or tsu (BC2)
trec (W)
(Note5)
S2
(Note5) (Note7) (Note6) (Note5) (Note5)
W# DQ1~16
(Word Mode)
tsu (D)
DATA IN STABLE
th (D)
(Note5)
DQ1~8
(Byte Mode)
Note 5: Hatching indicates the state is "don't care". Note 6: A Write occurs during S1# low, S2 high ov erlaps BC1# and/or BC2# low and W# low. Note 7: When the f alling edge of W# is simultaneously or prior to the f alling edge of BC1# and/or BC2# or the f alling edge of S1# or rising edge of S2, the outputs are maintained in the high impedance state. Note 8: Don't apply inv erted phase signal externally when DQ pin is in output mode.
7
2002.9.3 Ver. 0.0
MITSUBISHI LSIs
M5M5W817KT - 70HI
8388608-BIT (524288-WORD BY 16-BIT / 10485776-WORD BY 8-BIT) CMOS STATIC RAM
Write cycle (S1# control mode)
A0~18
(Word Mode)
tCW
A-1~18
(Byte Mode)
BC1#, BC2#
(Note5)
tsu (A)
tsu (S1)
trec (W)
(Note5)
S1#
S2
(Note5) (Note7) (Note5)
W#
(Note5)
(Note6)
DQ1~16
(Word Mode)
tsu (D)
DATA IN STABLE
th (D)
(Note5)
DQ1~8
(Byte Mode)
Write cycle (S2 control mode)
A0~18
(Word Mode)
tCW
A-1~18
(Byte Mode)
BC1#, BC2#
(Note5)
tsu (A) S1#
(Note5)
tsu (S2)
trec (W)
(Note5)
(Note5)
S2
(Note7)
W#
(Note5)
(Note6)
DQ1~16
(Word Mode)
tsu (D)
DATA IN STABLE
th (D)
(Note5)
DQ1~8
(Byte Mode)
8
2002.9.3 Ver. 0.0
MITSUBISHI LSIs
M5M5W817KT - 70HI
8388608-BIT (524288-WORD BY 16-BIT / 10485776-WORD BY 8-BIT) CMOS STATIC RAM
POWER DOWN CHARACTERISTICS (1) ELECTRICAL CHARACTERISTICS (Ta=-40~85C, Vcc=2.7V~3.6V,unless otherwise noted)
Symbol Vcc Parameter Test conditions Min Limits Ty p Max Units V V V
(PD) Power down supply voltage Byte control input BC1# & BC2#
2.0 2.0 2.0 0.2
Vcc=2.0V (1) S1# > Vcc - 0.2V, BYTE# > Vcc - 0.2V or < 0.2V other inputs = 0 ~ Vcc (2) S2 < 0.2V , BYTE# > Vcc - 0.2V or < 0.2V other inputs = 0 ~ Vcc (3) BC1# and BC2# > Vcc - 0.2V S1# < 0.2V, S2 > Vcc - 0.2V BYTE# > Vcc - 0.2V or < 0.2V other inputs = 0 ~ Vcc
VI (BC) VI (S1#) VI (S2)
Chip select input S1# Chip select input S2
~ +25C ~ +40C ~ +70C ~ +85C
-
0.2 0.4 -
3.0 6.0 30 60 A
Icc
(PD)
Power down supply c urrent
(2) TIMING REQUIREMENTS
Symbol Parameter Power down set up time Power down recov ery t ime
Note 9: Typical parameter of Icc(PD) indicates the value for the center of distribution at 2.0V, and not 100% tested.
Test conditions
Min
Limits Ty p
Max
Units ns ms
tsu (PD) trec (PD)
0 5
(3) TIMING DIAGRAM
BC# control mode Vcc note10:On the BC# control mode, the lev el of S1# and S2 must be f ixed
at S1#, S2 > Vcc-0.2V or S2 <0.2V
tsu (PD) 2.2V BC1# BC2# S1# control mode Vcc
2.7V
2.7V
trec (PD) 2.2V
BC1# , BC2# > Vcc - 0.2V note11:On the S1# control mode, the lev el of S2 must be f ixed
at S2 > Vcc-0.2V or S2 <0.2V
tsu (PD) 2.2V S1# S2 control mode Vcc S2 0.2V tsu (PD)
2.7V
2.7V
trec (PD) 2.2V
S1# > Vcc - 0.2V
2.7V
2.7V
trec (PD) 0.2V
S2 < 0.2V
9
2002.9.3 Ver. 0.0
MITSUBISHI LSIs
M5M5W817KT - 70HI
8388608-BIT (524288-WORD BY 16-BIT / 10485776-WORD BY 8-BIT) CMOS STATIC RAM
Keep safety first in your circuit designs!
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products betterand more reliable, but there isalways the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
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